Implantable stimulation devices deliver electrical stimuli to nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder subluxation, etc. The description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability with any implantable medical.
An SCS system typically includes an Implantable Pulse Generator (IPG) 10 shown in plan and cross-sectional views in FIGS. 1A and 1B. The IPG 10 includes a biocompatible device case 30 that holds the circuitry and battery 36 necessary for the IPG to function. The IPG 10 is coupled to electrodes 16 via one or more electrode leads 14 that form an electrode array 12. The electrodes 16 are configured to contact a patient's tissue and are carried on a flexible body 18, which also houses the individual lead wires 20 coupled to each electrode 16. The lead wires 20 are also coupled to proximal contacts 22, which are insertable into lead connectors 24 fixed in a header 28 on the IPG 10, which header can comprise an epoxy for example. Once inserted, the proximal contacts 22 connect to header contacts 26, which are in turn coupled by feedthrough pins 34 through a case feedthrough 32 to circuitry within the case 30.
In the illustrated IPG 10, there are thirty-two lead electrodes (E1-E32) split between four leads 14, with the header 28 containing a 2×2 array of lead connectors 24. However, the number of leads and electrodes in an IPG is application specific and therefore can vary. In a SCS application, the electrode leads 14 are typically implanted proximate to the dura in a patient's spinal cord, and when a four-lead IPG 10 is used, these leads are usually split with two on each of the right and left sides of the dura. The proximal electrodes 22 are tunneled through the patient's tissue to a distant location such as the buttocks where the IPG case 30 is implanted, at which point they are coupled to the lead connectors 24. A four-lead IPG 10 can also be used for Deep Brain Stimulation (DBS) in another example. In other IPG examples designed for implantation directly at a site requiring stimulation, the IPG can be lead-less, having electrodes 16 instead appearing on the body of the IPG for contacting the patient's tissue.
As shown in the cross section of FIG. 1B, the IPG 10 includes a printed circuit board (PCB) 40. Electrically coupled to the PCB 40 are the battery 36, which in this example is rechargeable (36r); other circuitry 50a and 50b coupled to top and bottom surfaces of the PCB; a telemetry coil 42 for wirelessly communicating with an external controller (not shown); a charging coil 44 for wirelessly receiving a magnetic charging field from an external charger 90 (FIG. 2) for recharging the battery 36; and the feedthrough pins 34 (connection not shown). (Further details concerning operation of the coils 42 and 44 and the external devices with which they communicate can be found in U.S. Patent Application Ser. No. 61/877,871, filed Sep. 13, 2013).
An issue requiring care in an IPG 10, especially one in which the battery 36 is rechargeable, is design of the battery management circuitry, which is described in one example in commonly-owned U.S. Patent Application Publication 2013/0023943, which is incorporated herein by reference in its entirety. FIG. 2 shows the battery management circuitry 84 disclosed in the '943 Publication, which is briefly discussed. Rechargeable battery 36r may comprise a Li-ion polymer battery, which when fully charged can provide a voltage, Vbat(r), of about Vmax(r)=4.2 Volts. However, other rechargeable battery chemistries could be used for battery 36r as well.
As noted, an external charger 90, typically a hand-held, battery-powered device, produces a magnetic non-data-modulated charging field 98 (e.g., 80 kHz) from a coil 92. The magnetic field 98 is met in the IPG 10 by front-end charging circuitry 96, where it induces a current in the charging coil 44 in the IPG 10. This induced current is rectified 46 to a voltage V1, which is then filtered (by a capacitor) and limited in its magnitude (by a Zener diode, e.g., to 5.5V), and passed through a back-flow-prevention diode 48 to produce a DC voltage, Vdc. Transistors 102 coupled to the charging coil 44 can be controlled by the IPG 10 (via control signal LSK) to transmit data back to the external charger 90 during production of the magnetic field 98 via Load Shift Keying, as is well known.
As discussed in the '943 Publication, Vdc is provided to battery management circuitry 84, which may reside on an Application Specific Integrated Circuit (ASIC) along with other circuitry necessary for IPG 10 operation, including current generation circuitry (used to provide specified currents to selected ones of the electrodes 16); telemetry circuitry (for modulating and demodulating data associated with telemetry coil 42 of FIG. 1B); various measurement and generator circuits; system memory; etc. The front-end charging circuitry 96 and the battery 36r typically comprise off-chip (off-ASIC) components, along with other electronics in the IPG 10, such as the telemetry coil 42; various DC-blocking capacitors coupled to the electrodes 16 (not shown); a microcontroller 100, which can communicate with the ASIC (and the battery management circuitry 84) via a digital bus 88; and other components of lesser relevance here. Microcontroller 100 may comprise in one example Part Number MSP430, manufactured by Texas Instruments, which is described in data sheets at http://www.ti.com/lsds/ti/microcontroller/16-bit_msp430/overview.page? DCMP=MCU_other& HQS=msp430, which is incorporated herein by reference. The ASIC may be as described in U.S. Patent Application Publication 2012/0095529, which is also incorporated herein by reference.
The battery management circuitry 84 in FIG. 2 is comprised of two circuit blocks: charging circuitry 80 for generating a current for charging the battery 36r, and load isolation circuitry 82 for controllably connecting or disconnecting the battery 36r from the load 75 that the battery 36r powers during normal operation of the IPG 10. Load 75 can comprise both on-chip (on-ASIC) circuit blocks such as the current generation circuitry and the telemetry circuitry mentioned earlier, and off-chip (off-ASIC) components such as the microcontroller 100.
As depicted, the charging circuitry 80, the load isolation circuitry 82, and the battery 36r generally have a T-shaped topology, with the charging circuitry 80 intervening between the front-end charging circuitry 96 (Vdc) and the positive terminal (Vbat(r)) of the battery 36r, and with the load isolation circuitry 82 intervening between Vbat(r) and the load 75.
As discussed in the '943 Publication, the load isolation circuitry 82 can prohibit the battery 36r (Vbat(r)) from being passed to power the load (Vload) dependent on a number of conditions. For example, if the load 75 is drawing a significantly high current (as indicated by overcurrent detection circuitry 74 via assertion of control signal OI); if Vbat(r) is too low (as indicated by rechargeable battery undervoltage detector 70 via assertion of a rechargeable battery undervoltage control signal UV(r)); or if an external magnetic field signal μ is indicated by a Reed switch 78 (e.g., in an emergency condition warranting presentation by the patient of an external shut-off magnet), the load 75 will be decoupled from Vbat(r) via switches 62 or 64. Load isolation circuitry 82 is discussed in further detail in the above-incorporated '943 Publication. Discharge circuitry 68 is also provided to intentionally drain the battery 36r if Vbat(r) is too high.
The charging circuitry 80 begins at Vdc—the DC-voltage produced by the front-end charging circuitry 96 in response to the external charger 90's magnetic field 98. Vdc splits into two paths in the charging circuitry 80 that are connected in parallel between Vdc and Vbat(r): a trickle charging path, and an active charging path, either of which can be used to provide a charging current (Ibat) to the battery 36r. 
The trickle charging path is passive, i.e., its operation is not controlled by control signals, and requires no power other than that provided by Vdc to produce a charging current (Itrickle) for the battery 36r. As shown, the trickle charging path presents Vdc to a current-limiting resistor 50 and one or more diodes 52, and is used to provide a small charging current, Itrickle, to the battery 36r. Using a small trickle charging current is particularly useful when the battery 36r is significantly depleted, i.e., if Vbat(r) is below a threshold Vt1, such as 2.7V for example.
To produce Itrickle, Vdc must be higher than the sum of the voltage drops across the resistor 50 and diode(s) 52 and the voltage of the battery 36r, Vbat(r). If Vdc is small (perhaps because the coupling between the external charger 90 and the IPG 10 is poor) or non-existent, diodes 52 will prevent the battery 36r from draining backwards through the trickle charging path. Itrickle is generally on the order of ten milliamps. This is desirably small, because a significantly depleted rechargeable battery 36r can be damaged if it receives charging currents (Ibat) that are too high, as is well known.
The active charging path proceeds in FIG. 2 from Vdc to the battery 36r through a current/voltage source 56, which is used to produce charging current Iactive. In the example of FIG. 2, the active charging path also passes through control and protective measures for the battery management circuitry 84, including a charging current sense resistor 58 used in conjunction with a charging current detector 72, and an overvoltage protection switch 60 used in conjunction with an overvoltage detector 66 to open circuit the active charging path if the battery voltage, Vbat(r), exceeds a maximum value (such as Vmax(r)=4.2V).
Circuitry for the current/voltage source 56 in the active charging path is shown in FIG. 3A. As its name implies, source 56 can be controlled to provide either a constant current or a constant voltage to the battery 36r during active charging. The source 56 comprises a current mirror comprised of P-channel transistors 104 and 106, which receive Vdc and a reference current, Iref, provided by a current source 110 in reference current generator circuitry 113. Current mirror control transistor 104 mirrors a representation of Iref in current mirror output transistor(s) 106 to produce the active charging current, Iactive. In the example shown, M output transistors 106 are wired in parallel, and thus the current provided by output transistor(s) 106 equals Iactive=M*Iref. A single wider output transistor 106 (M times wider than the current mirror control transistor 104) could also be used.
The current source 110 used to produce Iref is adjustable via control signals Itrim[2:0], and also comprises a current mirror. As shown, a system reference current, I′ (e.g., 100 nA), is mirrored transistors 116, 118, and 120, each of which are coupled in series to gating transistors controlled by the Itrim control signals. Transistors 116, 118, and 120 are preferably of different widths, or comprise different numbers of transistors in parallel, to provide different contributions to Iref. For example, transistors 116, 118, and 120 may respectively contribute I′*N, I′*2N, and I′*4N to Iref, thus allowing Iref to vary from I′*N to I′*7N in increments of I′*N, depending on which control signals Itrim0, Itrim1, and Itrim2 are active. Additional Itrim control signals and additional current mirror output transistors (e.g., 116-120) could be used to control Iref over a wider range, and/or with smaller resolution. Adjusting Iref in this manner in turn adjusts Iactive via operation of the current mirror transistor 104 and 106 discussed above.
Control signals Itrim are issued by a source controller 86. As shown at the bottom of FIG. 3A, the source controller 86 communicates with the microcontroller 100 by a digital bus 88, and so the microcontroller 100 can control the source controller 86 to in turn control the source 56 via Itrim and other control signals discussed further below.
The mode in which the source 56 operates to generate a charging current depends on the magnitude of the battery voltage, Vbat(r), which is known to the microcontroller 100. If the battery 36r is significantly depleted, i.e., Vbat(r)<Vt1 (e.g., 2.7), the microcontroller 100 commands the source controller 86 to disable the source 56. This occurs by the source controller 86 issuing charge enable control signal Ch_en=‘0’ to the reference current generator 113, which turns off N-channel transistor 108 and disables generation of the reference current, Iref, and hence Iactive. Thus, the battery 36r in this circumstance can only be charged via the trickle charging path, and only if magnetic field 98 and Vdc are present and sufficient.
If Vbat(r)>Vt1, but below an upper threshold Vt2 described further below (i.e., if Vt1<Vbat(r)<Vt2), the source 56 operates in a constant current mode. In this mode, Ch_en=‘1’, and transistor 108 allows Iref and hence Iactive to flow with a magnitude ultimately set by the Itrim control signals. When source 56 operates in constant current mode, Iactive is generally on the order of 50 milliamps. A P-channel transistor 114 in the active current path is fully on in constant current mode, thus allowing Iactive to flow to the battery 36r without resistance.
If Vbat(r)>Vt2 (e.g., 4.0 V), the source 56 operates in a constant voltage mode. Ch_en and the Itrim control signals are still asserted in this mode. Crossing of the Vt2 threshold and switching of charging modes is affected via rechargeable voltage measurement circuitry 111 in the source 56. Vbat(r) is determined in this circuitry 111 via a high-impedance resistor ladder, which produces a voltage Va indicative of Vbat(r). Va and a known band-gap reference voltage, Vref(a), are compared at a comparator 112. When Va>Vref(a), indicating that Vbat(r)>Vt2, the comparator 112 starts to turn off transistor 114, and the source 56 operates in constant voltage mode, providing an essentially constant voltage to the positive terminal of the battery 36r. As the internal cell voltage of the battery 36r increases in this mode, its internal resistance causes Iactive to fall off exponentially, until Vbat(r) reaches a maximum value, Vmax(r) (e.g., 4.2V). At this point, the microcontroller 100 will consider charging of the battery 36r to be complete, and will once again assert Ch_en=‘0’ to curtail further active charging. (Additionally, overvoltage switch 60 may also be opened). By contrast, when Va<Vref(a), indicating that Vbat(r)<Vt2, the comparator 112 turns on P-channel transistor 114, and the source 56 operates in constant current mode as described earlier. Voltage Va can be trimmed as necessary using control signals Vtrim to trim the resistance in the ladder, which essentially sets threshold Vt2.
FIG. 3B generally illustrates operation of the charging circuitry 80 to produce the charging current (Ibat) received by a severely depleted battery 36r (i.e., where Vbat(r) is below an even lower threshold Vuv(r)=2.0V) as a function of time during a charging session, including the trickle, constant current, and constant voltage modes enabled by the charging circuitry 80 as described above. Also shown are typical values for the charging current in each of these modes, and the capacity of the battery 36r illustrated as a percentage.
The battery management circuitry 84 of FIG. 2 provides additional safeguards as discussed in the '943 Publication. For example, diode(s) 54, preferably matching diode(s) 52 in number, are connected between the trickle and active charging paths, which ensure that both the source and drain of the overvoltage switch 60 are biased to the same voltage—to Vbat(r)—even when Vbat(r) is low. Diode(s) 54 thus protect the battery 36r from inadvertently discharging through overvoltage switch 60, particularly at the inopportune time when Vbat(r) is already low, and when it therefore might be difficult to provide a suitably high voltage to the gate of P-channel transistor 60 to turn it off.
The problem of low levels for Vbat(r) is significant. If Vbat(r) is severely depleted, i.e., if Vbat(r)<Vuv(r)=2.0V for example, it may be difficult to recover (recharge) the battery 36r by traditional charging techniques. This is because rechargeable batteries are unable to handle large charging currents without damage, and Itrickle, as passively set by the resistance R of the components (50, 52) in the trickle charging path, may be too large when Vbat(r)<Vuv(r). This problem is exacerbated the lower Vbat(r) becomes.
As discussed above, one solution to the problem of battery depletion is to decouple the battery 36r from the load 75 via the load isolation circuitry 82 to prevent the battery from being further depleted by the load. This is the function of the rechargeable battery undervoltage detector 70, which as disclosed in the '943 Publication is shown in FIG. 4. Note that the rechargeable battery undervoltage detector 70 receives no control signals and thus passively outputs a rechargeable battery undervoltage control signal UV(r), which is preferred because this circuit must work reliably at low levels for Vbat(r) when control signals may not be trustworthy. When Vbat(r)>Vuv(r), the voltage divider formed by diodes 122 and resistor 124 forms a suitably high voltage at the gate of N-channel transistor 128 to turn it on, which pulls UV(r) to ‘0’. By contrast, when Vbat(r)<Vuv(r), the voltage at the gate of transistor 128 is not high enough to turn on that transistor. UV(r) is thus pulled to ‘1’ (i.e., to Vbat(r)) through a pull-up resistor 126. Both of resistors 124 and 126 are in the range of tens of M-ohms. The forward drop across the diode(s) 122 (as well as their number) and the resistor 124 effectively operate to set the value of threshold Vuv(r). Although not shown, control signal UV(r) may be buffered at the output of the rechargeable battery undervoltage detector 70 to improve its integrity. When UV(r)=‘1’ during a rechargeable battery undervoltage condition, both of the P-channel load isolation switches 62 and 64 (FIG. 2) are off, thus isolating the battery 36r and preventing further depletion.
However, decoupling the battery from the load 75 during a rechargeable battery undervoltage condition brings other problems. The load 75 includes all of the remaining circuitry in the IPG, including the microcontroller 100 and the ASIC, which are completely shut down. Once power is eventually restored to these circuits, their state may be uncertain. For example, the inventors consider it particularly unfortunate that the timing (clock) circuitry in the IPG can lose its time basis, such that when the timing circuitry is later powered (assuming the battery 36r is eventually recharged), the timing circuitry will be reset to zero. Because various data is logged and stored with timestamps for later review, having an unreliable timestamp makes it difficult to review data spanning such a loss of time basis. See, e.g., U.S. Pat. No. 8,065,019 (discussing a solution to this problem involving time basis resetting in the IPG using timestamps provided wirelessly by an external device).
Plus, it may simply be difficult to reliably decouple the load 75 using the load isolation switches 62 and 64 if Vbat(r) is very low (e.g., <1.0 V). This is because the load switches 62 and 64 comprise P-channel transistors, which require a high signal (‘1’) to turn these transistors off. However, if Vbat(r) drops to very low levels, it cannot be guaranteed that control signal UV(r) can be generated by the rechargeable battery undervoltage detector 70 (FIG. 4) to a voltage sufficient to turn load isolation switches 62 and 64 off, taking the thresholds of those switches into account. This could cause discharging of the battery through the load isolation switches 62 and 64 and the load 75 at the very time when Vbat(r) is already very low and battery depletion is least desired.
Despite the protections provided in the '943 Publication to keep the battery 36r from depleting to severe levels, such depletion is still possible, and the ability to recovery the battery made more difficult during subsequent charging sessions. Solutions to these problems are disclosed herein.